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Sony 3ClearVid CMOS Technology Primer

Oct 23, 2006 12:59 PM, Steve Mullen

In this installment of HDV@Work, we look at the technology behind Sony's ClearVid CMOS chips, found in the new HVR-V1U camcorder. In the last installment, we looked at five aspects of CMOS technology. First, we looked at how CMOS chips function. Second, we saw how exposure control is implemented — including how the ability to simultaneously read multiple elements from a CMOS chip reduces the possibility of the “rolling shutter” artifact. Third, Correlated Double Sampling (CDS) was shown to be a common method of reducing Fixed Pattern Noise (FPN) that results from each CMOS element having its own on-chip amplifier. Fourth, we explored how extra circuits on a chip can increase latitude. (ClearVid does not use this technology.) Last, we learned that the chip element-count determines the cut-off frequency for the anti-alias low-pass filter that is what really limits image resolution.

In the illustration below, we can see that only a portion of a CMOS element actually captures light. The area of the photodiode divided by the element’s total area is called its “fill factor.” (It’s possible that when Sony claims V1’s ClearVid elements have the “same area” as the Z1’s CCD elements, they are talking about fill factor percentages.)

Most CMOS imagers today use Active Pixel Sensor technology (APS), which requires at least three transistors to implement. (These are called 3T devices.) There is no reason to believe ClearVid is any different. Sony illustrates its ClearVid technology using the diagram below.

Each CMOS element is rotated 45 degrees. Despite the rotation, the elements are “square.” Because the ClearVid chips used in the V1/FX7 have a resolution of about 1000x1000 and have a 16:9 aspect ratio, we know the idealized elements above cannot be an accurate representation.

ClearVid elements most likely look like the squat diamond shown below. The photodiode area is shown outlined in yellow. (This example has about a 33-percent fill factor. Sony claims a very high fill factor.)

In my crude diagram below, you can see how such an element can support an equal number of elements on each axis and fill a 16:9 space.

Despite the rotation of elements, elements are read out row-by-row as shown below. Elements are read out into Sony’s Enhanced Image Processing chip (EIP).

According to Sony Japan, four elements — from four columns — are read simultaneously from each ClearVid chip into each of the EIP’s three 2-million cell buffers. By outputting four elements at a time, read-out speed is increased by a factor of four, thereby eliminating, or at least significantly reducing, the rolling-shutter artifact. (Read-out speed is “X” in the last installment’s section on exposure control.)

When a row is output, each element sends its signal down its column bus where it is input to a Sample & Hold circuit that briefly stores the value. (There is a Sample & Hold for each column.) Next, a second cycle is performed on the same row. Immediately, all row elements are sent down to a second set of Sample & Hold circuits. The second set of values is measures of each element’s inherent noise. The first set of values is measures of element signal+noise values. Now all stored noise values are subtracted from all signal+noise values to yield a row of signal values. This system is called Correlated Double Sampling (CDS). Sony uses this type of CDS. The output from a ClearVid chip is an analog signal that is converted to a digital signal by a 14-bit A-to-D converter in the Digital eXtended Processor (DXP). The DXP chip uses 14-bit words for baseband signal processing — for example, for noise reduction.

The diagram below shows eight elements that lie in two rows. The elements in odd rows — labeled A, B, C, and D — are read out simultaneously. This occurs 135 times for the 540 elements in each row. All elements in Row 1 are read out before all elements in Row 2 are read out.

The elements in even rows — labeled W, X, Y, and Z — are also read out simultaneously. Again, this occurs 135 times for the 540 elements in each even row.

The first two rows to be read out are Rows 1 and 2. The next rows to be read out are Rows 3 and 4. The read-out process works down the chip as shown below.

The last two rows that are read-out are Rows 1080 and 1081. By the end of this process, all 960 elements in each of the 1081 rows have been read out and transferred into the EIP’s buffer.

Traditionally we consider an image sensor to be the device in which an image forms and from which it is captured. In my effort to understand ClearVid technology, I considered each 2 million-cell buffer to be a “Virtual Sensor.” In my view, the process by which a Virtual Sensor is filled — and the way pixels in a VS are processed — explain how the V1/FX7 camcorder’s measured resolution derives from the 980x1080 ClearVid chips. My theory is more complex than the “interpolation” explanation offered by Sony.

Study the diagram below to see how Rows 1 through 9 from a ClearVid chip may be mapped into upper 8 lines of a Virtual Sensor (VS).

First, note that the top line in a VS contains elements from the top two rows from a ClearVid sensor. Elements 1A, 1B, 1C, and 1D from Row 1 are first placed into Line 1. Next, elements 2W, 2X, 2Y, and 2Z from Row 2 are placed into Line 1. Also, note that each of the samples from the CMOS sensor is placed into alternating cells. Therefore, two rows of 540 elements fill 50 percent of one line of a Virtual Sensor.

Second, note that in Line 2, 540 new samples (3A, 3B, 3C, and 3D) are input from Row 3. And, 540-samples (2W, 2X, 2Y, and 2Z) are copied from Line 1. As all rows are transferred into a VS, 540 new samples are input, and 540 samples are copied from the previous line. This process continues until all 1080 lines in a Virtual Sensor have been filled.

This possible ClearVid-chip-to-Virtual-Sensor mapping enables 1 million CMOS elements to be transferred into a 2 million-cell Virtual Sensor. We are not, however, simply interested in filling a 1920x1080 Virtual Sensor with 1 million samples. We are interested in how this mapping process affects vertical resolution.

In interlace mode, each second, 60 progressive frames are transferred from a ClearVid chip to a Virtual Sensor buffer. These frames become interlaced video by creating and encoding odd lines from the odd frames into odd fields and even lines from the even frames into even fields. However, to eliminate line flicker and line twitter, it is critical that these lines pass through a low-pass filter to reduce effective vertical resolution by 25 percent. This, of course, is normally accomplished by Row-Pair summation, performed as 540 lines are read out from a CCD to create a single 1080i field.

No Row-Pair summation was performed during the CMOS read out process. However, if you look closely at the diagram below, you will see that in the mapping process, each line in a Virtual Sensor is composed of two ClearVid rows.

Line 2 has elements from Rows 2 and 3 while Line 3 has elements from 3 and 4. By using a “sliding” Row-Pair process during the mapping process, a low-pass filter function is executed that eliminates line flicker and line twitter. Reports place the camcorder’s effective vertical resolution at approximately 700 TV lines. Given this measure, and a Kell Factor of 0.85, the low-pass filter lowers vertical resolution by 25 percent. (Using my math model of 12 HD camcorders, the V1’s resolution should be 807x692. My model’s total average error for all 12 camcorders is 0.25 pixels.)

To record progressive video, the three CMOS sensors send 24, 25, or 30 frames to the three VS buffers. Traditionally, progressive video is not filtered — although to prevent Moiré patterns, a switchable filter is often provided. (Notice the pattern created on the fine horizontal lines of the white blinds.)

The V1 always passes 75 percent of potential CMOS chip resolution. Therefore, effective vertical resolution — and light sensitivity — is identical for both progressive and interlace video.

The reported effective horizontal resolution of the V1/FX1 is approximately 800-TVL/ph for both interlace and progressive video. Therefore, the process used to fill the empty cells in a Virtual Sensor increases effective horizontal resolution by 1.75X. (Using a Kell Factor of 0.85.) In my opinion, the interpolation process used is a four-tap 2D FIR (yellow cells around the green cell in diagram above — Sony’s diagram is below) implemented by a FPGA (Field Programmable Gate Array). Of course, before MPEG-2 encoding, the 1920 pixels are scaled to 1440 pixels, after which each field is encoded.

Through a combination of mapping and interpolation processes, the 960x1080 elements in a ClearVid CMOS chip are converted to 1920x1080 pixels in a Virtual Sensor that yield an image with an effective resolution of 800x700. Interestingly, this is about the same resolution reported for a Canon camcorder that uses three 1440x1080-element CCDs.

From all the questions raised about 3ClearVid image resolution, you might think resolution was the most important aspect of the new V1/FX1. After extensive hands-on testing of the V1, I have found there are equally important virtues provided by 3ClearVid technology. We will examine several in the next HDV@Work newsletter installment.

Continue the discussion on “Crosstalk” the Millimeter Forum.
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