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MillimeterCMOS Technology Primer
Oct 9, 2006 1:33 PM, By Steve Mullen
CMOS imagers, like CCDs, are made from silicon. CMOS, which stands for Complementary Metal Oxide Semiconductor, also is used to describe the manufacturing process. Today CMOS is the most common method of making processors and memories. Therefore, CMOS imagers take advantage of the high-volume process and cost advancements created by other CMOS devices (such as cell phone cameras).
While CMOS imagers are inexpensive, they suffer from Fixed Pattern Noise (FPN) that results from each element having its own amplifier. Each amplifier may have slightly different offset and gain characteristics. These amplifiers will impose the same noise pattern on every image.
Look closely at the illustration below. The only area of a pixel that collects light is the “photodiode.” The area of the photodiode divided by the pixel’s total area is called the “fill factor.” Depending on the number of transistors employed in each pixel, the fill factor can either be small or even smaller. A fill-factor of 30 to 25 percent is common.
Most CMOS imagers today use Active Pixel Sensor technology (APS), which requires at least three transistors to implement. (These are called 3T devices.) The pixel features: a reset transistor, an amplifier transistor, and a row-select transistor (Column Bus transistor).
Each capture cycle begins when a pulse is sent to the reset transistors in a row to prepare the photodiodes to capture light. After resetting all pixels in a row, the amount of light falling on the photodiode determines how much charge accumulates in the Potential Well. Technically, the reset begins an “integration” period.
Exposure Control
Each row, from top to bottom, is reset sequentially over a very short time, “Z” milliseconds. The exposure time, “Y,” begins when the middle row is reset. Shortly before the end of the exposure time — for example, 1/60 second — sequentially from top to bottom, row-select transistors are switched on, connecting each pixel’s amplifier transistor to its column bus. (A chip has a column bus, as you would expect, for every chip column. More later.) The integration period for a row ends when the row-select transistors are switched on.
The time required to row-by-row connect all rows to their columns is “X” and is determined by how fast the chip can read out all rows from the CMOS chip. This rate is the chip’s read-out clock rate. CMOS sensors can output data very rapidly. Because Z is equal to X, total image exposure time, Y, ends when the middle row’s pixels are selected to be sent down the chip’s columns.
The top-to-bottom exposure operates essentially as does a “vertical focal plane” shutter in a 35mm camera. The first (red) curtain is released to start its downward travel at the beginning of the exposure time. As the curtain moves, downward, the film is exposed to light.
When the first curtain has completed its travel, the film frame is fully exposed. When the exposure time ends, the second curtain (green) is released to begin its downward travel to close off light falling on the film. For a fast shutter speed, the first curtain may not have traveled far before the second curtain starts chasing it down the frame. The film, therefore, will be exposed by a narrow traveling slit formed by the gap between the two curtains. This slit can create the “rolling shutter” artifact as shown below.
The key to reducing this artifact is to design chips that are able to read out all rows very rapidly. This reduces the value of X. Of course, doing so requires a very high read-out clock rate. The higher the rate, the more power consumed and heat that must be dissipated. One solution is to divide the chip in half and read out pixels from both halves simultaneously. This requires dual output ports.
Short exposures are simple to accomplish because row-select transistors are switched on very quickly after the reset pulse. To support longer than, for example, a 1/60 second shutter, the imager chip and DSP must operate asynchronously because the DSP output frame rate must match that of the recording system.
For example, for 60i recording, whenever a longer-than-1/60-second exposure period ends, the frame is read out and into the DSP in a manner that does not disturb the output of the current frame to the recording system. This task becomes more complicated when a shutter time is not an integral of the DSP frame rate. For example, for a 1/48 second (20.8ms) shutter, transfer from chip to DSP can only occur on 16.7ms boundaries.
Image Read Out
When the row-select transistors are switched on in each row, each pixel’s amplifier transistor converts the accumulated charge to a voltage that is sent down its column bus, where it is input to a Sample & Hold circuit that briefly stores the value. (There is a Sample & Hold for each column.)
Next, a second cycle is performed on the selected row, staring with a second pulse to the reset transistors. Immediately, all row-select transistors are switched on, connecting each amplifier transistor to its column so all row pixels are sent down to a second set of Sample & Hold circuits.
The second set of values is a measure of each pixel’s voltage when no light has been captured. It is a measure of each pixel’s inherent noise. The first set of values are measures of pixel signal+noise values. Now all stored noise values are subtracted from all signal+noise values to yield a row of signal values. This system is called Correlated Double Sampling (CDS). The diagram below shows this type of CMOS chip operation.
All column signal values are loaded into a shift register, where analog pixel information is serially shifted to an internal analog-to-digital (A/D) converter.
There are alternate versions of this design. First, the A/D converter may not be on the chip, in which case the output is like that from a CCD — an analog signal. Second, the subtraction may not occur within the chip. In this case, the signal+noise and the noise values are output simultaneously. Again, it is possible to output these two values as digital data or analog signals.
Dynamic Range
CMOS sensors, compared to CCDs, have several unique characteristics. For example, they have no vertical smear.
CMOS sensors can also act in very intelligent ways. For example, CMOS can capture a very wide-latitude picture. It does so by snapping two pictures for each required output frame. One picture has a longer integration time that is ideal for capturing shadow detail. The other picture has a shorter integration time that is ideal for capturing very bright details. This process is called Dual Sampling.
This complex process can be implemented using an APS 3T design. First, row n is read out (long exposure) down the column busses and into Sample & Hold circuits at the top of the imager. Second, row n+ is read out (short exposure) down the column busses and into Sample & Hold circuits at the bottom of the imager. When the chip reads out data, it serially pulls pairs of values from the top and bottom Sample & Hold circuits.
Amazingly, while the pair of rows read out are of different integration times, they are not of the same row. Therefore, the DSP must assemble the incoming rows into a coherent image that has extended dynamic range. The major drawback of dual sampling is the use of only two integration times. Illumination levels that do not fit into one of these integration times will be captured with reduced signal-to-noise ratio.
Can Dual Sampling be accomplished with Correlated Double Sampling? The answer is yes under either of two conditions. One, if CDS is implemented within the chip, then the signal from each row already has the noise values subtracted from the signal+noise values. (This requires two upper and two lower Sample & Hold circuits, plus subtraction circuits.) Alternately, if the chip can read out four signals simultaneously to the DSP, the DSP can assemble the incoming rows into an image while subtracting noise values from signal+noise values.
CMOS Resolution
The number of pixels on each axis of any imager determines the “sampling frequency” of each axis. Based on the Nyquist Theorem, the sampling frequency of each axis must be at least twice the frequency (i.e., detail size) of the image’s resolution. Image frequencies (detail) above this limit must be removed by a low-pass filter to prevent aliasing artifacts from appearing in the captured image. Both optical and electronic anti-aliasing filters are employed. Once these anti-aliasing filters have eliminated fine picture detail, it is gone and cannot be recorded.
With this background, in the next HDV@Work newsletter we will apply these concept to understanding Sony’s 3X ClearVid sensor technology. I’ll also provide a “hands-on” report of my experience with an HVR-V1U. Then in November, we’ll return to our series on working with multi-format HDV.
Continue the discussion on “Crosstalk” the Millimeter Forum.
